`timescale 1ns/1ps

module tb_alu;

logic                      clk             ;
logic                      rst_n           ;
logic                      pd_rst          ;
logic                      alu_req         ;
logic                      alu_ctrl_land   ;
logic                      alu_ctrl_lor    ;
logic                      alu_ctrl_lxor   ;
logic                      alu_ctrl_sll    ;
logic                      alu_ctrl_srl    ;
logic                      alu_ctrl_sra    ;
logic                      alu_ctrl_add    ;
logic                      alu_ctrl_sub    ;
logic                      alu_ctrl_slt    ;
logic                      alu_ctrl_unsign ;
logic[6:0]                 alu_ctrl_inst_id;
logic[31:0]                alu_op1_val     ;
logic[31:0]                alu_op2_val     ;
logic[5:0]                 alu_rd_ind      ;
logic                      alu_resp_vld    ;
logic[5:0]                 alu_resp_rd_ind ;
logic[31:0]                alu_resp_rd_val ;
logic[6:0]                 alu_resp_inst_id;
logic                      alu_fwd_vld     ;
logic[5:0]                 alu_fwd_rd_ind  ;
logic[31:0]                alu_fwd_rd_val  ;
logic[6:0]                 alu_fwd_inst_id ;


frv_iu_alu _frv_iu_alu(
.clk             (clk             ),
.rst_n           (rst_n           ),
.pd_rst          (pd_rst          ),
.alu_req         (alu_req         ),
.alu_ctrl_land   (alu_ctrl_land   ),
.alu_ctrl_lor    (alu_ctrl_lor    ),
.alu_ctrl_lxor   (alu_ctrl_lxor   ),
.alu_ctrl_sll    (alu_ctrl_sll    ),
.alu_ctrl_srl    (alu_ctrl_srl    ),
.alu_ctrl_sra    (alu_ctrl_sra    ),
.alu_ctrl_add    (alu_ctrl_add    ),
.alu_ctrl_sub    (alu_ctrl_sub    ),
.alu_ctrl_slt    (alu_ctrl_slt    ),
.alu_ctrl_unsign (alu_ctrl_unsign ),
.alu_ctrl_inst_id(alu_ctrl_inst_id), 
.alu_op1_val     (alu_op1_val     ),
.alu_op2_val     (alu_op2_val     ),
.alu_rd_ind      (alu_rd_ind      ),
.alu_resp_vld    (alu_resp_vld    ),
.alu_resp_rd_ind (alu_resp_rd_ind ),
.alu_resp_rd_val (alu_resp_rd_val ),    
.alu_resp_inst_id(alu_resp_inst_id),    
.alu_fwd_vld     (alu_fwd_vld     ),
.alu_fwd_rd_ind  (alu_fwd_rd_ind  ),
.alu_fwd_rd_val  (alu_fwd_rd_val  ),    
.alu_fwd_inst_id (alu_fwd_inst_id )   
);

always #5 clk=~clk;

initial begin
    clk                 <= 0;
    rst_n               <= 0;
    pd_rst              <= 0;
    alu_req             <= 0;
    alu_ctrl_land       <= 0;
    alu_ctrl_lor        <= 0;
    alu_ctrl_lxor       <= 0;
    alu_ctrl_sll        <= 0;
    alu_ctrl_srl        <= 0;
    alu_ctrl_sra        <= 0;
    alu_ctrl_add        <= 0;
    alu_ctrl_sub        <= 0;
    alu_ctrl_slt        <= 0;
    alu_ctrl_unsign     <= 0;
    alu_ctrl_inst_id    <= 0;
    alu_op1_val         <= 0;
    alu_op2_val         <= 0;
    alu_rd_ind          <= 0;

    #15
    rst_n               <= 1;

    repeat(5) @(negedge clk);
    alu_req      <= 1;
    alu_ctrl_add <= 1;
    alu_op1_val  <= 3;
    alu_op2_val  <= 2;
    @(negedge clk);
    repeat(5) @(negedge clk);
    alu_req      <= 1;
    alu_ctrl_add <= 0;
    alu_ctrl_lor <= 1;
    alu_op1_val  <= 3;
    alu_op2_val  <= 2;
    repeat(5) @(negedge clk);
    alu_req      <= 1;
    alu_ctrl_lor <= 0;
    alu_ctrl_add <= 1;
    alu_op1_val  <= 3;
    alu_op2_val  <= 6;
    repeat(5) @(negedge clk);
    alu_req      <= 1;
    alu_ctrl_lor <= 1;
    alu_ctrl_add <= 0;
    alu_op1_val  <= 6;
    alu_op2_val  <= 6;
    repeat(5) @(negedge clk);
    alu_req      <= 0;
    alu_ctrl_lor <= 0;
    repeat(5) @(negedge clk);
    alu_req      <= 1;
    alu_ctrl_land<= 1;
    alu_ctrl_add <= 0;
    alu_op1_val  <= 7;
    alu_op2_val  <= 6;
    repeat(5) @(negedge clk);
    alu_req      <= 0;
    alu_ctrl_lor <= 0;
    repeat(5) @(negedge clk);

    $display("TEST PASS");
    // $dumpall;
    $finish;
end

endmodule